The present invention relates generally to memory devices and, more particularly, to an apparatus and method for low power, single-ended sensing in multi-port semiconductor memories using pre-discharged bit lines.
As integrated circuit (IC) technology dimensions continue to decrease, multi-port static random access memory (SRAM) structures are becoming more prevalent. Besides being able to perform multiple functions simultaneously within a single operation (e.g., reading and writing), multi-port SRAMs also provide the advantage that the read operation does not disturb the contents of the memory cell. This allows the basic six transistor (6T) storage cell and write port to be relatively stable and also writeable through use of write assist circuitry.
A typical 6T SRAM cell includes an array (rows, columns) of individual SRAM cells. Each SRAM cell is capable of storing a voltage value therein, which voltage value represents a corresponding binary logical data bit value (e.g., a “low” or “0” value, and a “high” or “1” value). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. Using CMOS (complementary metal oxide semiconductor) technology, each inverter comprises a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor, with the two transistors in each inverter typically connected in series between a positive voltage potential and ground. The inverters, further connected in a cross-coupled configuration, act as a bistable latch that stores the data bit therein so long as power is supplied to the memory array.
The typical SRAM cell also includes a read port, which can be dual-ended or single-ended. In dual-ended read ports, both the true and complement signal lines are generated within the cell and provided on local read bit lines through a column multiplexer to a sense amp. In single-ended read ports, only the true signal (or only the complement signal) is generated and sent to the sensing circuitry. Single-ended read port structures are significantly more area efficient than dual-ended read port structures because they require half the number of transistors per read port and half the number of signal lines. However, because they are single-ended, they cannot use common sense amp detection circuits, which require both true and complement signals. Hence, single-ended read port structures usually employ domino-type sensing circuitry in which the local read bit line is pre-charged to a high logic level and must be discharged to a low-enough voltage through the read port of the cell to activate the next stage. Because the read port devices are relatively small, the discharge rate of the local bit lines can be relatively slow. This limits the number of cells that can be placed on the local bit line and increases the number of domino sensing circuits required. This counteracts some of the area reduction benefit that single-ended designs provide. Dual-ended designs also pre-charge the local bit lines high, but because they are dual-ended, sense amp sensing circuits can be used to detect small voltage differences (usually 100 mV) between the true and complement signal lines. This can allow for faster operation, or more cells per local bit line.
The transistors within the typical SRAM cell exhibit relatively significant current leakage, particularly at the word-line transistor gates and the bit-line transistor gates. Since known SRAM cell designs require a constant power level both to maintain the data bit stored in the SRAM latch and to allow the reading from and the writing to of data, the current leakage increases the power used by the array of SRAM cells. For example, one common technique is to continuously pre-charge all of the read bit lines within the SRAM to a logical high level; for example, to a positive voltage of +1 volts. This is found in both dual- and single-ended read port structures. The pre-charge is done when the bit lines are not being accessed. After a read cycle involving selected read bit lines, the bit lines are returned to their pre-charge state. Also, since one local bit line per physical column is always discharged, AC power is consumed in recharging that local bit line. The resulting undesirable use of power in these prior art designs increases with the increase in SRAM cell density and the overall number of cells on an integrated circuit, such as a stand-alone memory device, or as part of a processor or application-specific integrated circuit (ASIC).
Various techniques to reduce the leakage current have been proposed, such as increasing the size of the cell by making the devices longer, increasing the threshold voltages of the cell, adding additional transistors to the cell, or lowering the voltage to the array when the cell is not being accessed. However, all of these techniques can increase the area of the array, or significantly reduce the performance of the array.
What is needed is an apparatus and method to reduce both the DC power consumption in a multi-port SRAM cell due to relatively large cell current leakage and as well as to reduce the AC power consumption in the multi-port SRAM cell due to relatively large bit line voltage swings, as also to reduce the area taken up by an SRAM cell on the IC.